The present invention relates to a drive apparatus for driving a charge coupled device (CCD) solid state image sensor, and, more particularly, to the stable operation of a CCD image sensor and cost reduction for the drive apparatus.
A frame transfer type CCD image sensor, which has the following advantages, is used in cameras or the like.
(1) The efficiency of using light is enhanced.
(2) It is easy to increase the pixel density (to increase the resolution).
The CCD image sensor includes an image sensing section, which performs photoelectric conversion, and a storage section, which is arranged separate from the image sensing section and temporarily stores charges acquired by the photoelectric conversion.
A frame transfer type CCD image sensor further includes a horizontal transfer section which outputs the charges stored in the storage section. The CCD image sensor repeats (1) vertical transfer for transferring the charges acquired by photoelectric conversion to the storage section from the image sensing section at a predetermined time period and (2) horizontal transfer for transferring the charges stored in the storage section to an output section row by row at a high speed.
A drive apparatus, which drives a frame transfer type CCD image sensor, includes a vertical driver, which applies a vertical transfer pulse signal to the image sensing section and storage section, and a horizontal driver, which applies a horizontal transfer pulse signal to the storage section and horizontal transfer section.
The drive apparatus further includes a timing control circuit which generates a timing clock signal in accordance with a system clock signal and provides the timing clock signal to the vertical and horizontal drivers. The timing clock signal determines the timing of generating pulse signals which are output from the vertical and horizontal drivers.
The pulse voltages of the pulse signals, which are output from the vertical and horizontal drivers, are set to a system voltage or a voltage which is acquired by stepping the system voltage up or down by using a power supply circuit.
In the frame transfer type CCD image sensor, applying the vertical transfer pulse signal to the image sensing section causes charges, which are acquired by photoelectric conversion, to be vertically transferred to the storage section from the image sensing section, and applying the horizontal transfer pulse signal to the horizontal transfer section causes horizontal transfer of the stored charges from the horizontal transfer section.
The vertical transfer of charges to the storage section requires a high voltage. Even with a required voltage supplied to the vertical driver from the power supply circuit, therefore, the voltage supplied from the power supply circuit temporarily drops at the time of vertical transfer. It takes a certain time for the dropped voltage to return to the desired voltage level. This affects the vertical transfer operation of the image sensing section.
This problem occurs in an interline type CCD image sensor as well as a frame transfer type CCD image sensor. The interline type CCD image sensor includes an image sensing stage, which performs photoelectric conversion, and a transfer stage, which is coupled in parallel to the image sensing stage and transfers charges, which are acquired by the photoelectric conversion, to a horizontal transfer section. The charge transfer by the transfer stage requires a high voltage, and a voltage supplied to an apparatus for driving the transfer stage also temporarily drops.
A drive circuit, which includes a vertical driver and a horizontal driver, and a power supply circuit are formed separately on a semiconductor integrated circuit substrate. This design is disadvantageous in reducing the yield of a drive apparatus, which includes the drive circuit and the power supply circuit, and cost increase of the drive apparatus. Further, the drive circuit and the power supply circuit, which are provided separately, should face restrictions on mounting on the substrate. This stands in the way of making a CCD-image-sensor drive apparatus compact.
FIG. 1 is a schematic circuit diagram of a buffer circuit 600 which is used in a CCD-image-sensor drive apparatus. The buffer circuit 600 includes an input inverter circuit 3 and an output CMOS inverter circuit 10. The inverter circuit 10 includes a P channel MOS (PMOS) transistor TRp and an N channel MOS (NMOS) transistor TRn connected in series. The source S of the PMOS transistor TRp is connected to a system supply voltage VDD and the source S of the NMOS transistor TRn is connected to ground GND.
An input signal IN, which is supplied to an input terminal 1, is output from an output terminal 2 with a delay of a predetermined time determined by the operational delays of the input inverter circuit 3 and the output CMOS inverter circuit 10. When the buffer circuit 600 is used as an output buffer, the transistors TRp and TRn are designed to have sizes (current capacities) according to a load which is connected to the output terminal 2.
Even with a simple circuit structure, the buffer circuit 600 can delay signals and drive a load. When the transistors TRp and TRn of the output CMOS inverter circuit 10 perform switching actions, however, a non-negligible through current flows through the transistors.
In a load-driving buffer circuit, particularly, the through current of the output CMOS inverter circuit is greater than the through current of a CMOS inverter circuit which is simply used in logic inversion. This inevitably increases the power consumption of a driver which uses a plurality of buffer circuits each having an output CMOS inverter circuit.
Accordingly, a first object of the present invention is to provide a drive apparatus that guarantees the stable operation of a CCD image sensor.
A second object of the present invention is to provide a buffer circuit having an output CMOS inverter circuit with reduced power consumption.
In a first aspect of the present invention, an apparatus for driving a CCD image sensor performing charge transfer operation in accordance with a pulse signal is provided. The apparatus includes a drive circuit for supplying a pulse signal to the CCD image sensor. A power supply circuit is connected to the drive circuit to supply the drive circuit with a voltage for generating the pulse signal. The power supply circuit includes an over-boosting circuit for temporarily over-boosting the voltage supplied to the drive circuit to generate an over-boosted voltage, prior to the charge transfer operation of the CCD image sensor.
In a second aspect of the present invention, an apparatus for driving a CCD image sensor performing charge transfer operation in accordance with a pulse signal is provided. The apparatus includes a drive circuit for supplying a pulse signal to the CCD image sensor. A power supply circuit is connected to the drive circuit to supply the drive circuit with a voltage for generating the pulse signal. The drive circuit and the power supply circuit are formed on a single semiconductor integrated circuit substrate.
In a third aspect of the present invention, a buffer circuit is provided. The buffer circuit includes a CMCS inverter circuit including a P channel MOS transistor and an N channel MOS transistor, which are connected in series. An input signal is supplied to gates of the P channel and N channel MOS transistors. A timing adjusting circuit is connected to the CMOS inverter circuit to adjust a timing of supplying the input signal to the gates of the P channel and N channel MOS transistors such that the P channel and N channel MOS transistors are turned on at different timings.
In a fourth aspect of the present invention, a driver is provided. The driver includes a plurality of functional circuits including a first functional circuit having a relatively high frequency of operations and a second functional circuit having a relatively low frequency of operations. The first functional circuit includes a first buffer circuit having a first CMOS inverter circuit having a first P channel MOS transistor and a first N channel MOS transistor, which are connected in series. A first timing adjusting circuit is connected to the first CMOS inverter circuit to supply first and second switching signals to gates of the first P channel MOS transistor and the first N channel MOS transistor such that in a period during which one of the first P channel and first N channel MOS transistors is turned off, the other one of the first P channel and first N channel MOS transistors is turned on. The second functional circuit includes a second buffer circuit having a second CMOS inverter circuit having a second P channel MOS transistor and a second N channel MOS transistor, which are connected in series. A second timing adjusting circuit is connected to the second CMOS inverter circuit to receive an input signal and supply a third switching signal to the gate of the second P channel MOS transistor such that an ON timing of the second P channel MOS transistor is delayed and an ON duration of the second P channel MOS transistor is shorter than an OFF duration of the second N channel MOS transistor. The second timing adjusting circuit supplies a fourth switching signal to the gate of the second N channel MOS transistor such that an ON timing of the second N channel MOS transistor is delayed and an ON duration of the second N channel MOS transistor is shorter than an OFF duration of the second P channel MOS transistor.
Other aspects and advantages of the invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.